The present invention generally relates to a method for processing an output signal of a charge-coupled device and an apparatus which implements the same. The present invention is suitable for application to a facsimile machine, an image scanner or the like.
Recently, a charge-coupled device (CCD) has widely been used. FIG. 1 illustrates a charge-coupled device which includes a CCD transfer channel and an output circuit. A CCD transfer channel 1 has a plurality of transfer electrodes 5. A detection diode 4 is provided in the vicinity of a transfer electrode 2. The detection diode 4 detects a signal charge transferred in synchronism with transfer clocks .phi..sub.1 and .phi..sub.2 and converts the signal charge into an output voltage. The transfer clocks .phi..sub.1 and .phi..sub.2 have an identical frequency and the mutually inverted phase. The signal charge transferred in synchronism with the transfer clocks .phi..sub.1 and .phi..sub.2 passes through the detection diode 4 for every period of each of the transfer clocks .phi..sub.1 and .phi..sub.2, so that the detection voltage drawn across the detection diode 4 varies on the basis of the current passing therethrough. A change in the detection voltage is applied to a buffer circuit 6, which outputs an output voltage Vs. The buffer circuit 6 is composed of a transistor and a resistor connected in series between a positive power source V.sub.DD and ground. A reset transistor 7 is connected between another positive power source V and the detection diode 4. A reset pulse .phi..sub.r which has a period identical to that of the transfer pulses .phi..sub.1 and .phi..sub.2 is applied to the gate of the reset transistor 7. When the reset transistor 7 is turned ON, the potential of the detection diode 4 is reset to be equal to the reference voltage V. The output circuit is formed on a common semiconductor substrate together with the CCD transfer channel 1. The arrangement shown in FIG. 1 is disclosed in Japanese Laid-Open Patent Application No. 63-208375. The output circuit shown in FIG. 1 is known as an on-chip-gate charge integrated type output circuit.
The on-chip-gate charge integrated type output circuit generates a reset noise caused by the reset transistor 7, as will described below. FIG. 2 is a waveform diagram of the output signal Vs from the output circuit. During time between t.sub.0 and t.sub.1, the reset pulse .phi..sub.r is being applied to the gate of the reset transistor 7 so that it is turned ON. The potential of the detection diode 4 is increased up to the drain voltage V of the reset transistor 7. At time t.sub.1, the reset transistor 7 is turned OFF. Thereby, the potential of the detection diode 4 becomes equal to a constant reference voltage Vo, which is based on a gate capacitance 8 equal to the sum of the capacitances of the detection diode 4 and the buffer circuit 6 as well as a gate-source capacitance of the reset transistor 7. At time t.sub.3, a charge is transferred to and passes through the detection diode 4 so that the output voltage Vs is obtained.
While the reset transistor 7 is conducting during the time between t.sub.0 and t.sub.1, the reset transistor 7 generates a reset noise En having a certain intensity. The reference voltage Vo is affected by the reset noise En so that it is varied. As shown in FIG. 2, each time the reset pulse .phi..sub.r is applied to the gate of the reset transistor 7, the reference voltage Vo is varied within a range between Vo .+-. Vn due to the presence of the reset noise En so that a signal-to-noise ratio (S/N ratio) of the output voltage Vs is deteriorated. It will be noted that Vn is the above-mentioned reset noise.
In addition to the reset transistor 7, the buffer circuit 6 shown in FIG. 1 is also a noise source which generates random noise. Random noise Er caused by the buffer circuit 6 has an amplitude which is inversely proportional to a reciprocal of a frequency f thereof, and is thus called 1/f noise.
In order to reduce the influence of the reset noise Vn and 1/f noise and improve the S/N ratio, a double correlation sampling method is known which the reference voltage Vo is clamped at a fixed potential at time t.sub.2 and the output voltage Vs is sampled at time t.sub.4.
However, the double correlation sampling method is capable of eliminating only low-frequency components of the reset noise En and the 1/f noise. Thus, the reference voltage Vo and the output voltage Vs are affected by random noises having no mutual relationship so that the S/N ratio of the output signal obtained by the double correlation sampling method Vs is deteriorated. In this case, random noises are 1/f noise or other high-frequency components.
That is, the double correlation sampling method is not capable of eliminating noises other than low-frequency components so that the S/N ratio of the output signal is deteriorated. From this viewpoint, there is a need to provide an improved process for eliminating all random noise components containing the reset noise and 1/f noise from the CCD output signal.